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VLSI Training in Pondicherry | Bangalore

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VLSI Digital Design using Verilog and hardware: Handson_temp

Course description

This course is a thorough introduction to the Verilog language. The emphasis is on writing Verilog model, both behavioral and structural source code and Register Transfer Level (RTL). This Sessions addresses targeting Xilinx FPGA devices . There is a lecture section for each main topic. This presents a basic foundation for the language. The Knowledge gained can be applied to any digital design by using a top-down or Bottom-up synthesis design approach. This course combines lectures with lab exercises to strengthen key concepts. You will also learn advanced coding techniques that will increase your overall Verilog.

Objective:

The Main goal of this course is to make you familiar with developing a RTL  Verilog model, both behavioral and structural, using as much of the language as possible, and writing a verification test cases and User constraints files for that model. 

Who should take this course?

This course is Designed for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And  Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs.

After the course  students with little Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and

Ø  Write RTL Verilog code for synthesis

Ø  Write Verilog test fixtures or Test benches  for simulation

Ø  Target and optimize Xilinx FPGAs by using Verilog

Ø  Run a timing simulation by using Xilinx  ISim  libraries

Ø  Create and manage designs within the Xilinx Design Suite

Ø  Correctly model combinational and sequential hardware blocks

Ø  Write User constraints files for any FPGA board.

What will students need to know or do before starting the course? :

Ø  Basic digital design knowledge

Software Tools

Ø  Download the Xilinx ISE Design suite 14.4 System Edition and Install In to your System.

Hardware

Ø  Digilent  NEXYS 2 Board   WITH Spartan 3E -500E or 1200 E .

 

What Will I Learn?

  • After the course students with little Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
  • Write Verilog test fixtures or Test benches for simulation
  • Run a timing simulation by using Xilinx ISim libraries
  • Correctly model combinational and sequential hardware blocks
  • Knowledge-intensive and industry-oriented program
  • Write RTL Verilog code for synthesis
  • Target and optimize Xilinx FPGAs by using Verilog
  • Create and manage designs within the Xilinx Design Suite
  • Write User constraints files for any FPGA board.

Curriculum For This Course

Introduction to Verilog

  1. Verilog Introduction : Verilog Definition, Verilog History, Level of Abstraction
  2. Verilog Introduction : (Continuation) Design Methodology, Modules
  3. Verilog Introduction : (Continuation) Lexical Conventions
  4. Verilog Introduction : (Continuation) Number Specification
  5. Verilog Introduction : (Continuation) Data Types
  6. Verilog Blocking and Non Blocking Assignments
  7. Verilog : Conditional Statements (If – Else)
  8. Verilog: Conditional Statements (Case)
  9. Verilog : Loop Statements
  10. Verilog : Coding Guidelines

Number Systems

  1. Number Systems: Definition and Radix Conversion
  2. Number Systems: Weighted codes, Non weighted Codes
  3. Number Systems: Gray Code, Gray Code Conversion, Error Detection Codes

Logic Gates

  1. Logic Gates: Theory: Logic gates_Introduction,Basic gates
  2. Logic Gates: Theory: Special pupose gates
  3. Logic Gates: Program
  4. Logic gates Program : TestBench and simulation Results
  5. Logic Gates: Hardware
  6. Assignment: Design the 2 input logic gates

Digital Design Combination:

  1. Multiplexer : Theory
  2. Multiplexer : Program
  3. Multiplexer: Program TestBench and simulation Results
  4. Multiplexer : Hardware
  5. Demultiplexer
  6. Encoders : Theory
  7. Encoders : Program
  8. Encoders: Program TestBench and simulation Results
  9. Encoder : Hardware
  10. Priority Encoders: Theory
  11. Priority Encoders: Program
  12. Priority Encoders: Program TestBench and simulation Results
  13. Priority Encoders: Hardware
  14. Decoders : Theory (Part 1)
  15. Decoders : Theory (Part 2)
  16. Decoders : Program
  17. Decoder Program : TestBench and simulation Results
  18. Decoders : Hardware
  19. Comparators : Theory
  20. Comparators : 2 Bit Program
  21. Comparators 2bit Program TestBench and Simulation Results
  22. Comparators : 2 Bit Hardware
  23. Comparators : nbits Program
  24. Majority Gate: Program
  25. Majority gate Program TestBench and Simulation Results
  26. Majority Gate: Hardware
  27. Arithmatic Circuits: Half Adder Theory
  28. Arithmatic Circuits: Full Adder Theory
  29. Arithmatic Circuits: Ripple Carry Adder Theory
  30. Arithmatic Circuits: Ripple Carry Adder Program
  31. Arithmatic Circuits: Ripple Carry adder Program TestBench and Simulation Result
  32. Arithmatic Circuits: Ripple Carry Adder Hardware
  33. Arithmatic Circuits: Universal Ripple Carry Adder Theory
  34. Code Converters : bin to bcd program
  35. Code Converters: bin to bcd program TestBench and simulation Results
  36. Code Converters : bin to bcd Hardware
  37. Code Converters : bin to gray program
  38. Code Converters : bin to gray program TestBench and simulation Results
  39. Code Converters : bin to gray Hardware
  40. Combinational circuits assignments

Digital Design Sequential

  1. Sequentail Circuits: Theory
  2. Flip Flops & Latches: SR Flip Flop Theory
  3. Flip Flops & Latches: SR Flip Flop Program
  4. Flip flops & Latchs : SR FlipFlop Program TestBench and simulation Results
  5. Flip Flops & Latches: SR Flip Flop Hardware
  6. Flip Flops & Latches: JK Flip Flop Theory
  7. Flip Flops & Latches: D Flip Flop Theory
  8. Flip Flops & Latches: D Flip Flop Program
  9. Flip Flops & Latches: D Flip Flop Hardware
  10. Registers : Theory
  11. Registers: SISO Theory
  12. Registers : SISO Program
  13. Registers: SISO program TestBench and simulation Results
  14. Registers : SISO Hardware
  15. Registers : SIPO Theory
  16. Registers : Theory
  17. Registers: SISO Theory
  18. Registers : SISO Program
  19. Registers: SISO program TestBench and simulation Results
  20. Registers : SISO Hardware
  21. Registers : SIPO Theory
  22. Registers : PIPO Program
  23. Registers : PIPO program TestBench and simulation Results
  24. Registers: SISO program TestBench and simulation Results
  25. Registers : PIPO Hardware
  26. Counters: Jhonson Counter Theory
  27. Counters: Jhonson Counter Program
  28. Counters : Jhonson counter program TestBench and simulation Results
  29. Counters: Jhonson Counter Hardware
  30. Counters: RING Counter Theory
  31. Counters: RING Counter Program
  32. Counters : Ring Counter Program TestBench and simulation Results
  33. Counters: RING Counter Hardware

Projects

  1. Design of SRAM in Verilog
  2. Design of SRAM in Verilog : Program
  3. Design of SRAM in Verilog : Program TestBench and Simulation
  4. FPGA Implementation of an Traffic Light Controller using Verilog HDL
  5. FPGA Implementation of Traffic Light: Program
  6. FPGA Implementation of Traffic Light : Program TestBench and Simulation
  7. FPGA Implementation of Traffic Light : Hardware
  8. DESIGN OF VGA DISPLAY SYSTEM BY USING FPGA
  9. Design of VGA Display System using FPGA: Program (1)
  10. Design of VGA Display System using FPGA: Program (2)
  11. FDesign of VGA Display System using FPGA: Program TestBench and Simulation(1)
  12. Design of VGA Display System using FPGA: Program TestBench and Simulation(2)
  13. Design of VGA Display System using FPGA: Hardware
  14. Verilog Programming On BASYS-3 with VIVADO.
  15. Verilog Programming On BASYS-3 with VIVADO_hardware

Requirements

  • Basics in any programming and part of Electronics

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